The present invention relates in general to non-volatile ferroelectric memory technology, and more particularly to an improved ferroelectric memory cell, its method of manufacture and method of operation as used in an array of such memory cells.
The ferroelectric random access memory (hereinafter referred to as “FeRAM”) has attracted considerable attention as next generation memory device because it has data processing speeds comparable to those of Dynamic Random Access Memories (hereinafter, referred to as “DRAMs”), and unlike DRAMs, conserves the data even after the power is turned off.
A unit cell of a conventional non-volatile FeRAM device comprises a switching element and a non-volatile ferroelectric capacitor. The switching element performs a switching operation depending on a state of a wordline to connect a non-volatile ferroelectric capacitor to a sub-bitline. The non-volatile ferroelectric capacitor is connected between a plate line and one terminal of the switching element. The switching element of the conventional FeRAM is a NMOS transistor whose switching operation is controlled by a gate control signal.
FIG. 1 is a cross-sectional diagram illustrating another conventional non-volatile ferroelectric memory device commonly referred to as one-transistor metal ferroelectric semiconductor field effect transistor (MFSFET). The one-transistor MFSFET cell comprises an N-type drain region 2 and an N-type source region 3 both formed in a P-type substrate 1. A ferroelectric layer 4 is formed on a channel region of the cell, and a gate (wordline) 5 is formed on ferroelectric layer 4.
Data is read from or written to the FeRAM cell using a channel resistance of the memory cell which varies depending on the polarization state of ferroelectric layer 4. For example, upon applying a negative voltage to gate 5, ferroelectric layer 4 is polarized such that positive charges are attracted to the channel region. The memory cell thus obtains a high resistance state, and would be in the off state when 0V is applied to gate 5. Conversely, upon applying a positive voltage to gate 5, ferroelectric layer 4 is polarized such that negative charges are attracted to the channel region. The memory cell thus obtains a low resistance state and would be in the on state when 0V is applied to gate 5.
However, these conventional non-volatile FeRAM cells suffer from a number of drawbacks. First, conventional MFSFET cells perform poorly where random access operation is required and also have poor data retention because of read and write disturbs present during operation. Also, the date retention is adversely impacted as the cell size is scaled down. Additionally, the crystal inconsistencies at the interface between ferroelectric film 5 and substrate silicon 1 require a special manufacturing process, thus increasing the process complexity and cost. The crystal inconsistencies also prevent reduction of the channel length and thus hinder scaling of the cell.
Accordingly, there is a need for an improved, versatile, and low cost FeRAM cell technology which enables scaling of the cell without impacting the performance characteristics of the memory device.